1. Field of the Invention
The present invention relates to a microcomputer incorporating a communication device capable of switching between two-wire two-way serial communication (two-wire full-duplex communication; UART) and single-wire two-way serial communication (single-wire half-duplex communication).
2. Description of the Prior Art
FIG. 12 is a block diagram of a conventional two-way communication device built in a microcomputer. In the figure, reference numeral 50 represents a two-way communication device, 2 a communication input terminal (R.times.D), 3 a communication output terminal (T.times.D), 4 a data bus terminal for communicating transmission and reception data with an external CPU, 5 a data bus in the device connected to this data bus terminal, 6 a reception shift register for storing communication input data inputted from the communication input terminal 2, 7 a reception buffer register for transferring data having a fixed number of bits stored in the reception shift register 6 to the data bus 5, 8 a transmission shift register for sending communication output data outputted to the communication output terminal 3, 9 a transmission buffer register for transferring data from the data bus 5 to the transmission shift register 8, 10 a baud rate generator for generating basic transmission and reception timings, 11 a reception clock control circuit for generating a reception clock as the basis of shift timing of the reception shift register 6 to control the reception shift register 6, 12 a divider for dividing the reception clock (into 1/16, for example) generated by the reception clock control circuit 11 to generate the shift timing of the reception shift register 6, 13 a transmission clock control circuit for generating a transmission clock as the basis of shift timing of the transmission shift register 8 to control the transmission shift register 8, 14 a divider for dividing the transmission clock (into 1/16, for example) generated by the transmission clock control circuit 13 to generate the shift timing of the transmission shift register 8, and 15 a reception permission flag for starting the monitoring of a start bit of the communication input data by a start bit detector 17, which is set from the data bus 5 by the external CPU. Reference numeral 16 represents a transmission permission flag for permitting the operation of the transmission clock control circuit 13, which is also set from the data bus 5. Denoted at 17 is a circuit for detecting the start bit of the communication input data of the communication input terminal 2, which activates the reception clock control circuit 11. Numeral 18 is a circuit for generating a start bit of the transmission shift register 8, which constantly sets the logic of the start bit at "Low".
The operation of the two-way communication device will be described hereafter. For two-way communication using a conventional two-way communication device 50, two two-way communication devices (communication devices 40 and 41) are connected with each other as shown in FIG. 13. In other words, the communication output terminal 3 of the device 40 is connected to the communication input terminal 2 of the device 41, and the communication output terminal 3 of the device 41 is connected to the communication input terminal 2 of the device 41. For two-way communication, communication data DATA-A1, DATA-A2 and DATA-A3 are transmitted from the device 40 to the device 41 at predetermined intervals and communication data DATA-B1, DATA-B2 and DATA-B3 are transmitted from the device 41 to the device 40 at predetermined intervals.
In this case, the first data are preset in the transmission buffer register 9 through the data bus 5, and the transmission request flag 16 and the reception permission flag 15 are set through the data bus 5 in each of the communication devices 40 and 41.
The set transmission request flag 16 enables the transmission clock control circuit 13 to operate and transfers data stored in the transmission buffer register 9 to the transmission shift register 8. The set transmission request flag 16 provides a clock generated by the baud rate generator 10 to the transmission clock divider 15 and the start bit generator 18. The start bit generator 18 sets the communication output terminal 3 at the "Low" level during a predetermined period of time. Thereafter, the transmission clock divider 14 generates a shift clock to the transmission shift register 8 and outputs the first transmission data to the communication output terminal 3.
Since the conventional two-way communication device is structured as described above, a two-wire two-way serial communication system or a single-wire two-way serial communication system is fixedly set in the device according to the user's specifications. Therefore, even if the user's specifications changed, the communication system could not be altered. In addition, the wiring costs of communication lines were high, and the circuit complicated.